2008 10 6

Design a verilog model of a half adder and write a testbench to verify the designed verilog model

module Add-half (sum,c_out,a,b);input a,b;output sum,c_out;wire c_out_bar;XOR (sum,a,b);nand (c_out_bar,a,b);not (c_out,c_out_bar);
endmodule