2008 10 20

module AOI_4_Unit(y_out,X_in1,X_in2,X_in3,X_in4);
input X_in1,X_in2,X_in3,X_in4;
output y_out;
wire y1,y2;
and #1 (y1,X_in1,X_in2);
and #1 (y2,X_in3,X_in4);
nor #1 (y_out,y1,y2);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always @(posedge clk)
if ($time > 1000) #(PERIOD-1) $stop;
endmodule

module test;
wire X_in1,X_in2,X_in3,X_in4;
wire y_out;

system_clock #100 clock1(X_in1);
system_clock #50 clock2(X_in2);
system_clock #20 clock3(X_in3);
system_clock #10 clock4(X_in4);

AOI_4_Unit AAA(y_out,X_in1,X_in2,X_in3,X_in4);

endmodule

這次的作業還算順利的做出來了

可能是上次有遇過的瓶頸突破了

覺得自己越來越有這方面的邏輯 很高興

module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;


xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule


module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

這次的project讓我了解了這次的作業並不相之前的那麼簡單了

跟很多同學討論 也讓我知道了更多

期待下個禮拜的上課

2008 10 6

Design a verilog model of a half adder and write a testbench to verify the designed verilog model

module Add-half (sum,c_out,a,b);input a,b;output sum,c_out;wire c_out_bar;XOR (sum,a,b);nand (c_out_bar,a,b);not (c_out,c_out_bar);
endmodule

實作

module top;wire a,b;reg c;System_clock #100 clock1(a);System_clock #50 clock2(b);always#1 c=a&b;endmodulemodule System_clock(clk);parameter PERIOD=100;output clk;reg clk;initialclk=0;alwaysbegin#(PERIOD/2)clk=~clk;#(PERIOD/2)clk=~clk;endalways@(posedge clk)if ($time>1000)#(PERIOD-1)$stop;endmodule

這次實作雖然只是把程式碼打上去但是也可以訓練打程式的細膩度期待下一次的實作